[PDF.61be] Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes

Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes

[PDF.nq02] Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes

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 | #4219800 in Books |  Springer |  2000-02-29 | Original language:English | PDF # 1 |  .91 x6.32 x9.32l, | File type: PDF | 272 pages

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||5 of 6 people found the following review helpful.| has practical tips, is shallow in giving understanding|By A Customer|The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking...

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